- An event-driven neural network on a mixed-signal neuromorphic processor was demonstrated for EEG-based epileptic seizure detection (Nature, 2025).1
- The approach enables on-device EEG analysis and a low-power, edge-deployable pipeline for physiological time series.1 1
Weekly enrichment (2026-07-20)
- The work was published in Scientific Reports (Nature portfolio journal; 2025, DOI 10.1038/s41598-025-99272-6) and proposes a novel two-layered spiking neural network (SNN) that amplifies and extracts the intrinsic partial synchronization (a “Chimera”-state signature) present but not prominent in EEG during seizure (ictal) periods.2
- The SNN was validated on a DYNAP-SE2 (Dynamic Neuromorphic Asynchronous Processor) mixed-signal neuromorphic chip using a full-custom hardware pipeline that requires no digital compute element in the loop.2
- Estimated on-chip SNN power consumption was about 150 µW on average across patients (roughly 2.8 µW per input channel) at a 1.8 V supply voltage.2
- The front end uses an analog front-end plus asynchronous delta modulation (ADM) to convert analog EEG directly into UP/DOWN spike events fed to the SNN, avoiding conventional high-rate clocked digital processing.2
- During seizures a subset of output-layer neurons increases firing to above 100 Hz while pre-seizure firing stays below that level, and a downstream linear Support Vector Machine (LSVM) classifier reliably separates ictal from non-ictal activity.2
- The authors released the event-based EEG seizure dataset and the synchronization-encoded spike trains publicly, positioning the framework as a step toward always-on “wear-and-forget” embedded seizure monitoring.2
- Context from related neuromorphic seizure work: a 34-neuron SNN on the DYNAP-SE1 chip detected chirps at the onset of all 40 seizures in 48 h of single-patient iEEG (100% sensitivity, one false alarm = 0.021/h), versus 80% sensitivity (32/40) for the software-only implementation.3
- Context on power efficiency: an earlier long-term iEEG neuromorphic study estimated average chip power as low as 12.48 µW, and related ECoG SNN hardware runs on a sub-milliwatt budget, reinforcing the low-power edge-monitoring appeal.45