- A Frontiers in Human Neuroscience paper applies polarity-considered EEG microstate labeling to stimulus-driven classification in an oddball paradigm, reporting improved classification accuracy versus approaches that ignore polarity in the stated framing.1
- The authors motivate BCIs as needing efficient feature extraction/dimensionality reduction from high-dimensional neural signals.1
- EEG microstate analysis assigns momentary scalp fields to a small set of spatial templates, described as relatively fast and noise-resistant.1
- Prior BCI microstate work often summarizes states with aggregate metrics (duration, occurrence frequency, coverage) rather than temporally ordered pointwise label sequences.1
- The study argues topography polarity is often ignored despite potential benefits for smoother transitions and better alignment with ERP structure.1
- The experiment used EEG from 40 healthy participants (20 per response-type group).1
- Templates were derived from the LEMON dataset via modified K-means clustering; incorporating polarity expands the standard 5 microstate maps (A–E) to 10 signed maps (A±, B±, C±, D±, E±), encoded as integers 0–9 for classification.1
- Adding polarity to the microstate labeling scheme improved classification F1 scores by approximately 19.8% in keyresTask and 19.5% in countTask (both p < 0.001, ηp² > 0.91), with the effect robust across all five non-K-means models.1
- The best-performing condition was cross-modal visual target (low-frequency visual with high-frequency auditory background); peak F1 reached 0.745 ± 0.025 at 275 ms in the key-response task using SVM.1
- Tree-based ensemble models (Random Forest, XGBoost, CatBoost) were the most stable; a six-model comparison also included SVM, Logistic Regression, and K-means across 5-fold cross-validation at 10 ms windows with 1 ms step size.1
- Real-time feasibility was demonstrated: microstate-to-prediction throughput exceeded 1.5 Mbps on a standard Windows laptop; approximate end-to-end latency was ~0.7 s post-stimulus, within practical P300-speller latency budgets.1
- Authors are affiliated with Nagaoka University of Technology (Engineering) and ATR’s Cognitive Mechanisms Laboratories (Kyoto), with a University of Tokyo co-author; the paper is positioned as a direct contribution toward P300-BCI speller applications.1